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Bài giảng Kỹ thuật số - Chương 6: VHDL

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VHDL  
- VHDL laø ngoân ngöõ moâ taû phaàn cöùng.  
- VHDL vieát taét cuûa VHSIC (Very High Speed Integrated  
Circuit) Hardware Description Language  
- VHDL khoâng phaân bieät chöõ vieát hoa vaø chöõ thöôøng.  
databus Databus DataBus DATABUS  
- VHDL laø ngoân ngöõ “ñònh daïng töï do”.  
if (a=b) then  
if (a=b)  
then  
if (a =  
b) then  
NguyenTrongLuat  
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Thuaät ngöõ COMPONENT:  
- Laø khaùi nieäm trung taâm moâ taû phaàn cöùng baèng VHDL ñeå bieåu  
dieãn caùc caáp thieát keá töø coång ñôn giaûn ñeán 1 heä thoáng phöùc taïp.  
- Moâ taû component bao goàm ENTITY vaø ARCHITECTURE.  
- Moät component coù theå söû duïng caùc component khaùc.  
mux2to1  
nand2  
d0  
a
b
y
z
d1  
sel  
NguyenTrongLuat  
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Maõ VHDL cô baûn  
LIBRARY  
khai baùo thö vieän  
ENTITY  
thöïc theå  
ARCHITECTURE  
kieán truùc  
NguyenTrongLuat  
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Ví duï: Maõ VHDL moâ taû component NAND 2 ngoõ vaøo  
LIBRARY ieee;  
USE ieee.std_logic_1164.all;  
ENTITY nand_gate IS  
PORT(  
a
a : IN STD_LOGIC;  
b : IN STD_LOGIC;  
z : OUT STD_LOGIC);  
z
b
END nand_gate;  
ARCHITECTURE model OF nand_gate IS  
BEGIN  
z <= a NAND b;  
END model;  
NguyenTrongLuat  
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LIBRARY ieee;  
USE ieee.std_logic_1164.all;  
LIBRARY  
- LIBRARY: khai baùo thö vieän ieee  
- USE: söû duïng caùc ñònh nghóa goùi (package) std_logic_1164  
ENTITY  
Moâ taû caùc tín hieäu xuaát/nhaäp cuûa khoái component  
ENTITY nand_gate IS  
PORT(  
a
b
a : IN STD_LOGIC;  
z
b : IN STD_LOGIC;  
z : OUT STD_LOGIC);  
END nand_gate;  
- ENTITY: ñaët teân cho entity (nand_gate)  
- PORT: khai baùo caùc chaân xuaát/nhaäp  
* Teân port (portname): a, b, z  
* Kieåu port (mode): IN, OUT  
* Kieåu tín hieäu (type): STD_LOGIC  
NguyenTrongLuat  
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* Caùc kieåu chaân PORT I/0  
IN: döõ lieäu ñi vaøo entity qua port vaø coù theå ñöôïc ñoïc trong entity.  
OUT:döõ lieäu xuaát ra ngoaøi entity qua chaân port.  
Port OUT khoâng theå ñoïc veà laïi entity.  
INOUT:laø port 2 chieàu, cho pheùp döõ lieäu ñi vaøo hoaëc ra.  
BUFFER:töông töï port OUT, nhöng ñöôïc pheùp ñoïc laïi bôûi entity.  
IN  
OUT  
BUFFER  
INOUT  
IN  
IN  
OUT  
NguyenTrongLuat  
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ARCHITECTURE  
Moâ taû thieát keá beân trong cuûa khoái, chæ roõ moái quan heä  
giöõa caùc ngoõ vaøo vaø ngoõ ra.  
ARCHITECTURE model OF nand_gate IS  
BEGIN  
z <= a NAND b;  
END model;  
a
z
b
- ARCHITECTURE: ñaët teân cho architecture (model)  
- Coù 3 loaïi moâ taû architecture  
* Moâ taû caáu truùc (Structural)  
* Moâ taû luoàng döõ lieäu (Dataflow)  
* Moâ taû haønh vi (Behavioral)  
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ÑOÁI TÖÔÏNG DÖÕ LIEÄU (Data object)  
* Tín hieäu (signal): bieåu dieãn cho caùc daây keát noái cuûa maïch.  
Noù ñöôïc khai baùo trong phaàn PORT cuûa khai baùo entity hoaëc  
trong phaàn ñaàu trong architecture (tröôùc BEGIN).  
SIGNAL signal_name : signal_type;  
SIGNAL a : std_logic;  
* Bieán (Variable): ñöôïc khai baùo vaø söû duïng trong process.  
Bieán khoâng phaûi laø tín hieäu logic thaät.  
VARIABLE variable_name : variable_type;  
VARIABLE b : std_logic;  
* Haèng soá (Constant): giöõ moät giaù trò khoâng ñöôïc thay ñoåi  
CONSTANT constant_name : constant_type;  
CONSTANT max : integer;  
Caùc ñoái töôïng döõ lieäu coù theå ñöôïc ñaët giaù trò ñaàu, khai baùo sau  
phaàn khai baùo kieåu döõ lieäu _type:= value;  
CONSTANT max : integer : = 25;  
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* Söï khaùc nhau giöõa Tín hieäu (Signal) vaø Bieán (Variable)  
- Leänh gaùn tín hieäu: signal_name <= expression;  
a <= NOT b AND c;  
variable_name := expression;  
- Leänh gaùn bieán:  
y := NOT a;  
- Pheùp gaùn bieán (Variable) cho giaù trò töùc thôøi, pheùp gaùn  
cuûa tín hieäu (signal) bò treã (delay)  
- Tín hieäu (Signal) coù theå quan saùt daïng soùng (waveform),  
nhöng bieán (Variable) thì khoâng.  
- Bieán (Variable) laø cuïc boä trong process.  
NguyenTrongLuat  
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KIEÅU DÖÕ LIEÄU (Data type)  
- Caùc kieåu döõ lieäu laø ñaëc tính cuûa signal, variable, …  
- Caùc döõ lieäu cuøng kieåu môùi ñöôïc gaùn hoaëc keát noái vôùi nhau  
- Coù theå taïo ra caùc kieåu döõ lieäu môùi baèng leänh TYPE hoaëc  
SUBTYPE  
* Kieåu BIT vaø BIT_VECTOR:  
- BIT coù giaù trò ‘0’ vaø ‘1’.  
- BIT_VECTOR laø daõy (array) cuûa BIT.  
* Kieåu INTEGER  
coù giaù trò TRUE vaø FALSE.  
* Kieåu BOOLEAN:  
* Kieåu CHARACTER  
* Kieåu lieät keâ (ENUMERATION) do ngöôøi söû duïng ñònh nghóa.  
* . . .  
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* STD_LOGIC:  
Value  
Meaning  
‘X’ Forcing (Strong driven) Unknown  
‘0’ Forcing (Strong driven) 0  
‘1’ Forcing (Strong driven) 1  
‘Z’ High Impedance  
- Laø kieåu tín hieäu quyeát  
ñònh (coù theå ñöôïc laùi baèng  
2 ngoõ vaøo)  
- Coù 9 giaù trò  
- Höõu ích khi moâ phoûng  
‘W’ Weak (Weakly driven) Unknown  
Weak (Weakly driven) 0.  
Models a pull down.  
Weak (Weakly driven) 1.  
Models a pull up.  
‘L’  
- Chæ coù 3 giaù trò ‘0’, ‘1’,  
‘Z’ laø coù theå toång hôïp  
‘H’  
‘-’ Don't Care  
‘U’ Uninitialized  
SIGNAL a: STD_LOGIC;  
a laø tín hieäu STD_LOGIC kieåu 1 bit  
SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0);  
SIGNAL c: STD_LOGIC_VECTOR(0 TO 7);  
b,c laø tín hieäu STD_LOGIC kieåu bus coù 8 bit  
NguyenTrongLuat  
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Pheùp gaùn tín hieäu kieåu STD_LOGIC  
SIGNAL a: STD_LOGIC;  
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);  
SIGNAL c: STD_LOGIC_VECTOR(0 TO 3);  
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);  
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);  
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);  
a <= ’1’;  
a <= b(2);  
-- giaù trò gaùn ñaët giöõa 1 daáu nhaùy ñôn ‘ ’  
-- a <= b(2),  
b <= "0000”;  
c <= B”0000”;  
d <= ”0110_0111”; -- bieåu dieãn töøng nhoùm 4 bit phaân caùch _  
-- giaù trò gaùn ñaët giöõa 1 daáu nhaùy keùp “ ”  
-- B laø kyù hieäu cô soá 2 (coù theå boû)  
e <= X”AF67”;  
f <= O”723”;  
b <= c;  
-- X laø kyù hieäu cô soá 16 (Hex)  
-- O laø kyù hieäu cô soá 8 (Octal)  
-- b(3) <= c(0), b(2) <= c(1),  
-- b(1) <= c(2), b(0) <= c(3)  
d(7 downto 6)<= ”11”;  
c(0 to 2)<= e(7 downto 5);  
NguyenTrongLuat  
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Gheùp noái chuoãi (Concatenation)  
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);  
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);  
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);  
a <= ”0000”;  
b <= ”1111”;  
c <= a & b;  
-- c = “00001111”  
-- d = “00001111”  
d <= ’0’ & ”0001111”;  
e <= ’0’ & ’0’ & ’0’ & ’0’ & ’1’ & ’1’ &  
’1’ & ’1’; -- e = “00001111”  
NguyenTrongLuat  
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PHEÙP TOAÙN (Operator)  
* Pheùp toaùn Logic (Logical Operator):  
NOT AND OR NAND NOR XOR XNOR  
Söû duïng cho kieåu: bit, bit_vector, boolean, std_logic, std_logic_vector.  
* Pheùp toaùn quan heä (Relationship Operator):  
= /= < <= > >=  
So saùnh 2 toaùn haïng cuøng kieåu vaø keát quaû traû veà kieåu boolean  
* Pheùp toaùn dòch (Shift Operator):  
SLL SRL SLA SRA ROL ROR  
* Pheùp toaùn coäng (Adding Operator):  
+ -  
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* Pheùp toaùn nhaân (Multiplying Operator):  
* / MOD REM  
- +  
** ABS  
* Pheùp toaùn daáu (Sign Operator):  
* Pheùp toaùn khaùc (Operator):  
* Thöù töï öu tieân thöïc hieän caùc pheùp toaùn  
** ABS NOT  
* / MOD REM  
+ - (Daáu)  
+ - &  
= /= < <= > >=  
AND OR NAND NOR XOR XNOR  
Caùc pheùp toaùn cuøng loaïi khoâng coù öu tieân, neáu caàn söû duïng ( )  
NguyenTrongLuat  
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MOÂ TAÛ THIEÁT KEÁ (Design description)  
MOÂ TAÛ THIEÁT KEÁ  
(Design description)  
CAÁU TRUÙC  
(Structural)  
LUOÀNG DÖÕ LIEÄU  
HAØNH VI  
(Behavioral)  
(Dataflow)  
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MOÂ TAÛ CAÁU TRUÙC (Structural description)  
- Söû duïng caùc khoái component coù caáp thaáp hôn.  
- Caùc khoái component naøy ñöôïc keát noái theo thöù baäc.  
- Caùc component caáp thaáp ñöôïc khai baùo baèng leänh  
COMPONENT, ñaët ôû phaàn ARCHITECTURE (tröôùc BEGIN).  
COMPONENT and2  
x1  
PORT (x1,x2:IN STD_LOGIC;  
y: OUT STD_LOGIC);  
END COMPONENT;  
y
x2  
- Ñeå keát noái component caáp thaáp, thöïc hieän leänh thay theá trò  
soá component (component instantiation) PORT MAP.  
Coù 2 caùch:  
* Keát hôïp vò trí (positional association)  
* Keát hôïp theo teân (named association)  
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* Keát hôïp theo teân (named association)  
COMPONENT component_name  
port declarations;  
END COMPONENT;  
...  
Label: component_name PORT MAP (  
port_name1 => sig_name1,  
port_name2 => sig_name2 );  
COMPONENT and2  
PORT (x1,x2:IN STD_LOGIC;  
y: OUT STD_LOGIC);  
END COMPONENT;  
BEGIN  
user1: and2 PORT MAP ( x1 => a, x2 => b,  
y => c );  
...  
NguyenTrongLuat  
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* Keát hôïp vò trí (positional association)  
COMPONENT component_name  
port declarations;  
END COMPONENT;  
...  
Label: component_name PORT MAP (  
sig_name1, sig_name2, ... );  
COMPONENT and2  
PORT (x1,x2:IN STD_LOGIC;  
y: OUT STD_LOGIC);  
END COMPONENT;  
BEGIN  
user1: and2 PORT MAP ( a, b, c );  
...  
NguyenTrongLuat  
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a
b
u1_out  
VD: Thieát keá XOR 3 ngoõ vaøo  
result  
LIBRARY ieee;  
USE ieee.std_logic_1164.all;  
c
ENTITY xor3 IS  
PORT ( a, b, c : IN STD_LOGIC;  
result : OUT STD_LOGIC);  
END xor3;  
ARCHITECTURE structural OF xor3 IS  
SIGNAL u1_out: STD_LOGIC;  
COMPONENT xor2  
PORT ( i1, i2 : IN STD_LOGIC;  
y : OUT STD_LOGIC );  
END COMPONENT;  
BEGIN  
u1: xor2 PORT MAP ( i1 => a, i2 => b,  
y => u1_out);  
u2: xor2 PORT MAP ( i1 => u1_out, i2 => c,  
y => result);  
END structural;  
NguyenTrongLuat  
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